Electronic design automation (EDA) systems provide software tools in which electronic circuit designs can be described, simulated, and translated by machine into a design realization. A conventional mechanism for describing a circuit design is hardware description language (HDL). A user defines a behavioral description of a design using HDL and the HDL design is processed to generate a physical implementation. HDL design tools include HDL simulation environments, such as the ModelSim environment from the Model Technology Company, and implementation environments, such as Synplify from Synplicity, Inc. Another type of circuit design system, referred to as a high level modeling system (HLMS), provides a higher level of abstraction for describing and simulating an electronic circuit than does an HDL simulation environment or implementation environment. An HLMS generally provides a mathematical representation of signals as compared to standard logic vectors in an HDL. It is desirable for the high-level abstractions to be precisely correlated with the ultimate implementation representation, both in simulation semantics and in implementation. The Xilinx System Generator for DSP and the MathWorks' Simulink and MATLAB environments are example HLMS's in which such capabilities are desirable.
A design implemented in an HLMS is typically simulated using software algorithms that model the hardware behavior of the blocks that comprise the model. Sometimes it is beneficial to use hardware, in addition to software, during a simulation. Using hardware in the simulation loop can accelerate simulation speeds dramatically, while also providing real-time hardware verification capabilities. The process of breaking a design into pieces and simulating those pieces using subsidiary design tools is referred to as “co-simulation.” When the subsidiary tool of interest is a reconfigurable hardware platform, the process is referred to as “hardware co-simulation.”
In hardware co-simulation, the simulation of a design under test (DUT) is offloaded to hardware. The host simulation environment (software) passes stimuli to the input ports of the DUT running on hardware via a communication interface. Similarly, the communication interface captures results from the output ports of the DUT and then reads the results back to the host simulation environment.
In particular, a design modeled in an HLMS is first compiled for a hardware co-simulation platform, during which a hardware implementation of the design is generated. The hardware co-simulation platform may include reconfigurable hardware, such as a field programmable gate array (FPGA) or other type of programmable logic device (PLD). In such case, the hardware implementation comprises a configuration bitstream. In the HLMS, the hardware implementation is associated with a co-simulation block, which is inserted into the model. The model is then simulated while the compiled design is actually executed on the hardware platform. The co-simulation block is essentially a front-end interface that fits into the HLMS framework, which imposes the form of blocks and diagrams on the co-simulation block. Underneath the co-simulation block, a hardware co-simulation engine serves as the backend and handles the communication with the hardware platform transparently. The hardware co-simulation block forwards simulation data to the hardware and reads back results to the HLMS.
A graphical block diagram environment of an HLMS provides an appealing visualization of abstracted system designs. However, such an environment may not be a suitable interface for every application. For example, a block diagram environment may not be a favorable choice for users who are more comfortable writing program code, or for external programs that integrate with hardware co-simulation programmatically. Creating test benches in a block diagram environment can sometimes be overwhelming. Debugging a design in a block diagram environment may require more effort. Accordingly, there exists a need in the art for a method and apparatus for providing hardware co-simulation interface that overcomes the aforementioned deficiencies.